>From owner-simulators Tue Mar 10 12:50:27 1998 Received: from meitner.cs.washington.edu (meitner.cs.washington.edu [128.95.2.104]) by june.cs.washington.edu (8.8.7+CS/7.2ju) with ESMTP id MAA00647 for ; Tue, 10 Mar 1998 12:50:27 -0800 Received: from meitner.cs.washington.edu (localhost [127.0.0.1]) by meitner.cs.washington.edu (8.8.5+CS/7.2ws+) with ESMTP id MAA24777 for ; Tue, 10 Mar 1998 12:50:27 -0800 (PST) Message-Id: <199803102050.MAA24777@meitner.cs.washington.edu> To: simulators@meitner.cs.washington.edu Subject: Intel binary translation patent Date: Tue, 10 Mar 1998 12:50:27 PST From: " pardo@cs.washington.edu" X-Message-Id: simulators@cs.washington.edu, message #1998-03-005 X-Unsubscribe: e-mail `majordomo@cs.washington.edu', body `unsubscribe simulators' X-URL: `http://www.cs.washington.edu/homes/pardo/sim.d/mail.d/index.html' It appears Intel has patented some aspects of ISA->ISA translation. Anybody who knows more, please let us know. http://techweb.cmp.com/eet/news/98/998news/intelreveals.html ... While Merced will take a hardware-conversion tack, it's clear that Intel is keeping its bases covered and is investigating a range of technologies for instruction-set conversion. Indeed, the picture that's emerging indicates that both hardware and software techniques may have a place in Intel's plans for a broad family of IA-64 microprocessors. "Remember, Epic is designed to be a highly scalable architecture," said [Rich] Belgard [patent consultant]. "At the cheapest level, you do a chip that handles translation in software. At the highest level, it happens all in hardware." Plans for a software-based approach are evident in Intel's new patent, awarded two weeks ago to Leonid Baraz and Yaron Farber, two Intel engineers based in the company's Haifa Design Center, in Israel. The patent, number 5,721,927, details a sophisticated method for performing, via software, a binary-to-binary conversion of one instruction language into another. "Computer program statements that have been decoded into machine instructions for a source instruction set, such as the Intel X86, may undergo a binary translation in order to be executed on a target instruction-set architecture, such as a RISC or a very-long-instruction-word (VLIW) architecture," the inventors note in their patent document. ... Belgard characterized the technique as "dynamic translation," which means that a program is translated on the fly. "While you're executing the program, the basic blocks of that program are being translated," he said. "It looks like there's going to be a task that's doing translation from X86 to native Merced instructions inside the processor. "It's not a fundamental patent," he added. "But it gives away the notion that they're going to be having a background task doing translation." Range Of Options While the software-translation technique will not be implemented on Merced, Curry asserted that Intel is "looking at various types of software translation, because we want software vendors to quickly get the maximum benefit out of the new [IA-64] architecture. "To get maximum performance for some 32-bit applications, you'll want to run the 64-bit instruction set, and we want to provide an easy means to do that." ... And: http://patents.uspto.gov/cgi-bin/ifetch4?INDEX+PATBIB-ALL+0+12339+0+6+20371+OF+1+1+1+5721927 Abstract A method for enabling a first block of instructions to verify whether the first block of instructions follows a second block of instructions in an order of execution. The method includes appending a compare instruction to the first block of instructions. The compare instruction compares a first value from the first block of instructions with a second value from the second block of instructions, which precedes the first block of instructions in the order of execution. The method further includes appending a branching instruction to the first block of instructions. The branching instruction is executed in response to the first value being unequal to the second value. The branching instruction, when executed, branches to an alternative look-up routine to obtain a block of instructions that follows the second block of instructions in the order of execution.