>From owner-simulators Mon Oct 23 17:32:24 1995 Received: from meitner.cs.washington.edu (meitner.cs.washington.edu [128.95.2.104]) by june.cs.washington.edu (8.6.12/7.2ju) with ESMTP id RAA16345; Mon, 23 Oct 1995 17:32:24 -0700 Received: from localhost (localhost [127.0.0.1]) by meitner.cs.washington.edu (8.6.12/7.2ws+) with SMTP id RAA23334; Mon, 23 Oct 1995 17:32:23 -0700 Message-Id: <199510240032.RAA23334@meitner.cs.washington.edu> To: rtcg@cs, simulators@cs Subject: [Barzilai et. al] HSS -- A High-Speed Simulator Date: Mon, 23 Oct 1995 17:32:23 PDT From: " pardo@cs.washington.edu" X-Message-Id: simulators@cs.washington.edu, message #1995-10-003 X-Unsubscribe: e-mail `majordomo@cs.washington.edu', body `unsubscribe simulators' X-URL: `http://www.cs.washington.edu/homes/pardo/sim.d/mail.d/index.html' %A Zeev Barzilai %A J. Lawrence Carter %A Barry K. Rosen %A Joseph D. Rutledge %T HSS\(emA High-Speed Simulator %J IEEE Transactions on Computer-Aided Design %D July 1987 %V CAD-6 %N 4 %P 601-617 %K multi-level %X ABSTRACT ``The High-Speed Simulator (HSS) is a fast and flexible system for gate-level fault simulation. Originally limited to combinational logic, it is being extended to handle sequential logci. ... The speed of HSS is obtained by converting the cycle-free portions of a circuit into optimized machine code for a general-purpose computer. This compiled code simulates the circuits response for 16 or 32 test patterns in parallel. Faults are injected into the circuit by changing the machine instructions corresponding to the fault location. From the range of speeds seen in recent measurements, we take 240 million gates per second as a fair general estimate of th speed of 2-valued simulation running on [an IBM] 3081/K computer. For 3-valued simulation, divide by 2.9. The paper discusses the merits and drawbacks of the HSS strategy [and extensions, directions for future work and lessons from long-term experience with HSS]. General idea: transform DAG circuit components into machine code. Evaluate the circuit by evaluating the machine code. Inject faults by modifying machine instructions to emulate the ``faulty'' behavior. (pg 602) HSS is a software simulator. The target machine is in the IBM System/370 family, but no special properties of the architecture are used. (pg 602) A test pattern is simulated by fist compiling the logic design into 370 machine instructions using a ``Generator Package''. (pg 603) Injecting faults via code modification ``may seem dangerous at first glance, but the actual implementation is systematic and easily maintained.'' (pg 606-607) The first generation simulator wrote a PL8 procedure containing a long series of assignment statements that applied basic Boolean operations to elements of arrays of words representing inputs and outputs and internal nets. Interspersed with the assignments were code to incorporate the fault model. For example, net[9] = input[2] & net[54] if (fault == 37) { net[9] = <> } else if (fault == 38) { net[9] = <> } In the second-generation simulator, the tests were omitted and the functionality was achieved by overwriting the assignment instructions as needed. The performance improves dramatically because few fault tests are taken, so most if tests are not taken. (pg 615) ``Because the user does not see major costs due to a capability unless that capability is being used, it has been possible to extend the original system in several directions without seriously degrading the speed and simplicity of the kind of job that provided the original motivation.'' (pg 610, 615) The Fourth-generation HSS simulator groups instructions and implements an event-driven simulator. Speedup of event-driven over oblivious simulation depends on how many gates ``fire'' at each cycle. The third-generation (oblivious) simulator is about 3,000 times faster than event-driven interpretive simulators. Fourth-generation simulator speedup unclear. One of the authors worked for the Eckert Mauchly Computer Company!